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mb96610 series f 2 mc - 16fx,16 - bit proprietary microcontroller cypress semiconductor corporation ? 198 champion court ? san jose, ca 95134 - 1709 ? 408 - 943 - 2600 document number: 002 - 04709 rev.*c revised july 11, 2017 mb96610 series is based on cypress advanced f 2 mc - 16fx architecture (16 - bit with instruction p ipeline for risc - like performance). the cpu uses the same instruction set as the established f 2 mc - 16lx family thus allowing for easy migration of f 2 mc - 16lx software to the new f 2 mc - 16fx products. f 2 mc - 16fx product improvements compared to the previous generation include significantly improved performance - even at the same operation frequency, re duced power consumption and faster start - up time.for high processing speed at optimized power consumption an internal pll can be selected to supply the cpu with up to 32mhz operation frequency from an external 4mhz to 8mhz resonator. the result is a minimu m instruction cycle time of 31.2ns going together with excellent emi behavior. the emitted power is minimized by the on - chip voltage regulator that reduces the internal cpu voltage. a flexible clock tree allows selecting suitable operation frequencies for peripheral resources independent of the cpu speed. features technology ? 0.18 m cmos cpu ? f 2 mc - 16fx cpu ? optimized instruction set for controller applications (bit, byte, word and long - word data types, 23 different addressing modes, barrel shift, variety of pointers) ? 8 - byte instruction queue ? signed multiply (16 - bit ? 16 - bit) and divide (32 - bit/16 - bit) instructions available system clock ? on - chip pll clock multipl ier ( ? 1 to ? 8, ? 1 when pll stop) ? 4 mhz to 8 mhz crystal oscillator (maximum frequency when using ceramic resonator depends on q - factor) ? up to 8 mhz external clock for devices with fast clock input feature ? 32 .76 8 khz subsystem quartz clock ? 100khz/2mhz internal rc clock for quick and safe startup, clock stop detection function , watchdog ? clock source selectable from mainclock oscillator , subclock oscillator and on - chip rc oscillator, independently for cpu and 2 clock domains of peripherals ? the subclock oscillator is enabled by the boot rom program controlled by a configuration marker after a power or external reset ? low power consumption - 13 operating modes (different run, sleep, timer, stop mode s ) on - chip voltage regulator ? internal voltage reg ulator supports a wide mcu supply voltage range (min=2.7v), offering low power consumption low voltage detection function ? reset is generated when supply voltage falls below programmable reference voltage code security ? protects flash memory content from un intended read - out dma ? automatic transfer function independent of cpu, can be assigned freely to resources interrupts ? fast interrupt processing ? 8 programmable priority levels ? non - maskable interrupt (nmi) can ? supports can protocol version 2.0 part a and b ? iso16845 certified ? bit rates up to 1m bps ? 32 message objects ? each message object has its own identifier mask ? programmable fifo mode (concatenation of message objects) ? maskable interrupt ? disabled automatic retransmission mode for time triggered can applicati ons ? programmable loop - back mode for self - test operation usart ? full duplex usarts (sci/lin) ? wide range of baud rate settings using a dedicated reload timer ? special synchronous options for adapting to different synchronous serial protocols
document number: 002 - 04709 rev.*c page 2 of 63 mb96610 serie s ? lin functionality working either as master or slave lin device ? extended support for lin - protocol to reduce interrupt load a/d converter ? sar - type ? 8/ 10 - bit resolution ? signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion mode , activation by software, external trigger , reload timers and ppgs ? range comparator function source clock timers ? three independent clock timers (23 - bit rc clock timer, 23 - bit main clock timer, 17 - bit sub clock timer) hardware watchdog timer ? hardware watchd og timer is active after reset ? window function of watchdog timer is used to select the lower window limit of the watchdog interval reload timers ? 16 - bit wide ? prescaler with 1/2 1 , 1/2 2 , 1/2 3 , 1/2 4 , 1/2 5 , 1/2 6 of peripheral clock frequency ? event count functio n free - running timers ? signals an interrupt on overflow , supports timer clear upon match with output compare (0, 4) ? prescaler with 1, 1/2 1 , 1/2 2 , 1/2 3 , 1/2 4 , 1/2 5 , 1/2 6 , 1/2 7 , 1/2 8 of peripheral clock frequency input capture units ? 16 - bit wide ? signals an int errupt upon external event ? rising edge, falling edge or both (rising & falling) edges sensitive output c ompare units ? 16 - bit wide ? signals an interrupt when a match with free - running timer occurs ? a pair of compare registers can be used to generate an output signal programmable pulse generator ? 16 - bit down counter, cycle and duty setting registers ? can be used as 2 8 - bit ppg ? interrupt at trigger, counter borrow and/or duty match ? pwm operation and one - shot operation ? internal prescaler allows 1, 1/4, 1/16, 1/64 o f peripheral clock as counter clock or of selected reload timer underflow as clock input ? can be triggered by software or reload timer ? can trigger adc conversion ? timing point capture quadrature position/revolution counter (qprc) ? up/down count mode, phase di fference count mode, count mode with direction ? 16 - bit position counter ? 16 - bit revolution counter ? two 16 - bit compare registers with interrupt ? detection edge of the three external event input pins ain, bin and zin is configurable real time clock ? operational on main oscillation (4mhz), sub oscillation (32khz) or rc oscillation (100khz/2mhz) ? capable to correct oscillation deviation of sub clock or rc oscillator clock (clock calibration) ? read/write accessible second/minute/hour registers ? can signal interrupts ev ery half second/second/minute/hour/day ? internal clock divider and prescaler provide exact 1s clock external interrupts ? edge or l evel sensitive ? interrupt mask bit per channel ? each available can channel rx has an external interrupt for wake - up ? selected usart channels sin have an external interrupt for wake - up non maskable interrupt ? disabled after reset, can be enabled by boot - rom depending on rom configuration block ? once enabled, can not be disabled other than by reset ? h igh or low level sensitive ? pin shared w ith external interrupt 0 i/o ports ? most of the external pins can be used as general purpose i/o ? all push - pull outputs ? bit - wise programmable as input/output or peripheral signal ? bit - wise programmable input enable ? one input level per gpio - pin (either automot ive or cmos hysteresis) ? bit - wise programmable pull - up resistor
document number: 002 - 04709 rev.*c page 3 of 63 mb96610 serie s built - in on chip debugger (ocd) ? one - wire debug tool interface ? break function: ? hardware break: 6 points (shared with code event) ? software break: 4096 points ? event function ? code event: 6 points (shared with hardware break) ? data event: 6 points ? event sequencer: 2 levels + reset ? execution time measurement function ? trace function: 42 branches ? security function flash memory ? dual operation flash allowing reading of one flash bank while programming or erasing the other bank ? command sequencer for automatic execution of programming algorithm and for supporting dma for programming of the flash memory ? supports automatic programming, embedded algorithm ? write/erase/erase - suspend/resume commands ? a flag indica ting completion of the automatic algorithm ? erase can be performed on each sector individually ? sector protection ? flash security feature to protect the content of the flash ? low voltage detection during flash erase or write
document number: 002 - 04709 rev.*c page 4 of 63 mb96610 serie s contents 1. product lineup ................................ ................................ ................................ ................................ .................... 6 2. block diagram ................................ ................................ ................................ ................................ ..................... 7 3. pin assig nment ................................ ................................ ................................ ................................ ................... 8 4. pin description ................................ ................................ ................................ ................................ .................... 9 5. pin circuit type ................................ ................................ ................................ ................................ ................. 11 6. i/o c ircuit type ................................ ................................ ................................ ................................ .................. 13 7. memory map ................................ ................................ ................................ ................................ ...................... 18 8. ramstart addresses ................................ ................................ ................................ ................................ ......... 19 9. user rom memory map for flash devices ................................ ................................ ................................ ..... 20 10. serial programming communication interface ................................ ................................ .............................. 21 11. interrupt vector table ................................ ................................ ................................ ................................ ....... 22 12. handling precautions ................................ ................................ ................................ ................................ ....... 26 12.1 precautions for product design ................................ ................................ ................................ ........................ 26 12.2 precautions for package mounting ................................ ................................ ................................ ................... 27 12.3 precautions for use environment ................................ ................................ ................................ ..................... 29 13. handling devices ................................ ................................ ................................ ................................ .............. 30 13.1 latch - up prevention ................................ ................................ ................................ ................................ .......... 30 13.2 unused pins handling ................................ ................................ ................................ ................................ ....... 30 13 .3 external clock usage ................................ ................................ ................................ ................................ ........ 30 13.3.1 single phase external clock for main oscillator ................................ ................................ ................................ .. 30 13.3.2 single phase external clock for sub oscillator ................................ ................................ ................................ ... 31 13.3.3 opposite phase external clock ................................ ................................ ................................ .......................... 31 13.4 notes on pll clock mode operation ................................ ................................ ................................ ................. 31 13.5 power supply pins (vcc/vss) ................................ ................................ ................................ ............................ 31 13.6 crystal oscillator and ceramic resonator circuit ................................ ................................ ................................ 31 13.7 turn on sequence of power suppl y to a/d converter and analog inputs ................................ ........................... 32 13.8 pin handling when not using the a/d converter ................................ ................................ ................................ 32 13.9 notes on power - on ................................ ................................ ................................ ................................ ........... 32 13.10 stabilization of power supply voltage ................................ ................................ ................................ ................ 32 13.11 serial communication ................................ ................................ ................................ ................................ ....... 32 13.12 mode pin (md) ................................ ................................ ................................ ................................ ................. 32 14. electrical characteristics ................................ ................................ ................................ ................................ . 33 14.1 absolute maximum ratings ................................ ................................ ................................ .............................. 33 14.2 recommended operating conditions ................................ ................................ ................................ ............... 35 14.3 dc characteristics ................................ ................................ ................................ ................................ ............ 36 14.3 .1 current rating ................................ ................................ ................................ ................................ ................... 36 14.3.2 pin characteristics ................................ ................................ ................................ ................................ ............ 39 14.4 ac characteristics ................................ ................................ ................................ ................................ ............ 40 14.4.1 main clock input characteristics ................................ ................................ ................................ ....................... 40 14.4.2 sub clock input characteristics ................................ ................................ ................................ ........................ 41 14.4.3 built - in rc oscillation characteristics ................................ ................................ ................................ ............... 42 14.4.4 internal clock timing ................................ ................................ ................................ ................................ ........ 42 14.4.5 operating conditions of pll ................................ ................................ ................................ ............................. 43 14.4.6 reset input ................................ ................................ ................................ ................................ ........................ 43 14.4.7 pow er - on reset timing ................................ ................................ ................................ ................................ ..... 44 14.4.8 usart timing ................................ ................................ ................................ ................................ .................. 45 14.4.9 external input timing ................................ ................................ ................................ ................................ ........ 47 14.5 a/d converter ................................ ................................ ................................ ................................ ................... 48 14.5.1 ele ctrical characteristics for the a/d converter ................................ ................................ ................................ 48
document number: 002 - 04709 rev.*c page 5 of 63 mb96610 serie s 14.5.2 accuracy and setting of the a/d converter sampling time ................................ ................................ .............. 49 14.5.3 definition of a/d converter terms ................................ ................................ ................................ .................... 49 14.6 low voltage detection function characteristics ................................ ................................ .............................. 52 14.7 flash memory write/erase characteristics ................................ ................................ ................................ ...... 54 15. example characteristics ................................ ................................ ................................ ................................ ... 55 16. ordering information ................................ ................................ ................................ ................................ ........ 58 17. package dimension ................................ ................................ ................................ ................................ .......... 59 18. major changes ................................ ................................ ................................ ................................ .................. 60 document history ................................ ................................ ................................ ................................ ...................... 62
document number: 002 - 04709 rev.*c page 6 of 63 mb96610 serie s 1. product lineup features mb96 610 remark product t ype flash memory p roduct subclock subclock can be set by software dual operation flash m emory ram - 32.5 kb + 32kb 4kb mb96f6 1 2 r, mb96f612a product options r: mcu with can a: mcu without can 64.5kb + 32kb 10 kb mb96f6 1 3 r, mb96f613a 128.5kb + 32kb 10 kb mb96f6 1 5 r, mb96f615a package lqfp - 48 lqa048 dma 2ch usart 3 ch lin - usart 2/7/8 with automatic lin - header transmission/reception yes (only 1ch) lin - usart 2 with 16 byte rx - and tx - fifo no 8/10 - bit a/d converter 1 6 ch an 0/1/3/4/6 to 10/ 12/14/16/24/25/30/31 with data buffer no with range comparator yes with scan disable no with adc pulse detection no 16 - bit reload timer (rlt) 3ch rlt 1/ 3 /6 16 - bit free - running timer (frt) 4 ch frt 0 to 3 frt 0 to 3 does not have external clock input pin 16 - bit input capture unit (icu) 7 ch ( 3 channels for lin - usart) icu 0/1/4 to 6/9/10 (icu 6/9/10 for lin - usart) 16 - bit output compare unit (ocu) 5 ch ocu 0/1/4/6/7 (ocu 4 for frt clear) 8/16 - bit programmable pulse generator (ppg) 8 ch (16 - bit) / 16 ch (8 - bit) ppg 0/1/3/4/6/7/12/14 with timing point capture yes with start delay no with ramp no quadrature position/revolution counter (qprc) 2ch qprc 0/1 can interface 1ch can 2 32 message buffers external interrupts (int) 11 ch int 0/2/3/4/7 to 13 non - maskable interrupt (nmi) 1ch real time clock (rtc) 1ch i/o ports 35 (dual clock mode) 37 (single clock mode) clock calibration unit (cal) 1ch clock output function 2ch low voltage detection function yes low v oltage d etection f unction can be disabled by software hardware watchdog timer yes on - chip rc - oscillator yes on - chip debugger yes note: ? all signals of the peripheral function in each product cannot be allocated by limiting the pins of package. it is necessary t o use the port relocate function of the g eneral i/o port according to your function use.
document number: 002 - 04709 rev.*c page 7 of 63 mb96610 serie s 2. block diagram m d interru p t controller dm a contro ll er peripheral bus 1 (clkp1) peripheral bus 2 (clkp2) i/o tim e r 3 f r t 3 icu 10 i/o tim e r 2 f r t 2 icu 9 i/o tim e r 1 f r t 1 icu 4/5/6 ocu 4 /6/7 i/o tim e r 0 f r t 0 icu 0/1 ocu 0 /1 16-bit reload timer 1/3/6 8/10-bit adc 16ch can interface 1ch usart 3ch pp g 8ch (16-bit) / 16ch (8-b i t) real t ime cloc k external interru p t 11ch q p r c 2ch vcc vss pp g 0, ppg1, p p g 3 , ppg4 o u t 0_r , o u t 1 _ r in0, in1 c peripheral bus bridg e peripheral bus bridg e 16 fx c o r e b u s ( cl kb ) tin1 t o t 1 , t o t3 a vcc a vss avrh an12, an14, a n 16 adtg_r an6 to an10 in4, in5 o u t 6, o ut7 int2_r, i nt4 _ r int7_r, i nt1 0_ r an24, an25 an30, an31 ra m b oot rom w a tc hdog v ol t age regulator sin2, sin2_r, s in7_r, sin8 _ r sot2, s o t 2_r, sot7 _ r, sot8 _ r sck2, sck2_r, sck7_r, sck8 _ r tx2 rx2 16fx cpu clock & mode cont r oller f la s h m e m o r y a nmi ain0, ain1 bin0, bin1 zin0, zin1 t t g 0, tt g 1, tt g 4, tt g 5 cko t 0_r, c k ot1, c k ot1 _ r ckotx1 x0, x 1 x 0 a, x 1a rstx pp g 6, ppg7, p p g 12, p p g 14 pp g 0_b, ppg1 _ b, pp g 3_b, p p g 4_b ppg6_b, ppg7 _ b, ppg12_b, p p g14_b t t g12, t t g1 3 int0, i n t8 to i n t13 int3_r1 oc d debu g i / f an0, an1, an3, an4 3ch
document number: 002 - 04709 rev.*c page 8 of 63 mb96610 serie s 3. pin assignment (top view) ( lqa048 ) * 1: cmos input level only * 2 : please set rom configuration block (rcb) to use the subclock. other than those above, general - purpose pins have only automotive input level. lqf p - 48 p0 1 _ 0 / t i n 1 / c k ot 1 / o u t 0 _r p 0 0 _ 3 / i n t 1 1 / sck 8 _r / p p g 3 _ b * 1 p0 0 _ 5 / i n t 13 / s i n 8 _ r / pp g 14 _ b * 1 p0 0 _ 4 / int12 / s o t 8 _r / p p g1 2 _ b p0 0 _ 2 / int10 / si n 7 _ r * 1 p0 0 _ 1 / i n t9 / s o t 7_ r / pp g 1_b p0 0 _ 0 / i n t8 / s c k 7_ r / pp g 0_b * 1 d eb u g i/f p1 7 _0 m d p0 4 _1 / x 1a * 2 p0 4 _0 / x 0a * 2 vss x 0 x 1 r s t x p0 2 _4 / a in0 / in0 / t t g0 p0 2 _2 / zi n 0 / pp g 14 / c k ot0_ r p0 2 _0 / pp g 12 / c k o t 1_ r p0 1 _7 / s c k 2 _ r / pp g 7_b * 1 p0 1 _6 / sot 2 _ r / pp g6_b p0 1 _5 / si n 2 _ r / i n t 7 _ r * 1 p0 1 _4 / pp g 4_b p 0 1 _1 / t o t 1 / c ko t x 1 / o u t 1_r vcc c p 0 2 _5 / bi n0 / i n1 / t t g 1 / a d t g _r p0 3 _0 / a i n1 / i n4 / t t g 4 / t t g 1 2 / an 24 p0 3 _1 / b i n1 / i n5 / t t g 5 / t t g 1 3 / an 25 p0 3 _ 2 / int1 0 _ r / r x 2 * 1 p0 3 _3 / t x 2 p 0 3 _ 6 / zi n1 / o u t 6 / a n30 p 0 3 _7 / o u t 7 / a n 31 p 0 6 _0 / a n 0 / p pg 0 p 0 6 _1 / a n 1 / p pg 1 a v cc a v ss a v rh p0 6 _ 3 / a n 3 / p pg 3 p0 6 _ 4 / a n 4 / p pg 4 p0 6 _ 6 / a n 6 / p pg 6 p0 6 _ 7 / a n 7 / p pg 7 p0 5 _0 / a n 8 / s i n 2 / i n t3 _ r 1 * 1 p0 5 _1 / a n 9 / s o t 2 p0 5 _2 / a n 10 / s c k2 * 1 p0 5 _4 / a n 12 / t o t 3 / i n t 2_ r p0 5 _ 6 / a n 14 / int4 _ r p0 7 _0 / a n 16 / int0 / n m i 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 36 3 5 3 4 3 3 32 31 3 0 29 2 8 2 7 26 25 1 2 3 4 5 6 7 8 9 10 1 1 12
document number: 002 - 04709 rev.*c page 9 of 63 mb96610 serie s 4. pin description pin name feature description adtg_r adc relocated a/d converter trigger input pin ainn qprc quadrature position/revolution counter unit n input pin ann adc a/d converter channel n input pin avcc supply analog circuits power supply pin avrh adc a/d converter high reference voltage input pin avss supply analog circuits power supply pin binn qprc quadrature position/revolution counter unit n input pin c voltage regulator internally regulated power supply stabilization capacitor pin ckotn clock output function clock output function n output pin ckotn_r clock output function relocated clock output function n output pin ckotxn clock output function clock output function n inverted output pin debug i/f ocd on chip debugger input/output pin inn icu input capture unit n input pin intn external interrupt external interrupt n input pin intn_r external interrupt relocated external interrupt n input pin intn_r1 external interrupt relocated external interrupt n input pin md core input pin for specifying the operating mode nmi external interrupt non - maskable interrupt input pin outn ocu output compare unit n waveform output pin outn_r ocu relocated output compare unit n waveform output pin pnn_m gpio general purpose i/o pin ppgn ppg programmable pulse generator n output pin (16bit/8bit) ppgn_b ppg programmable pulse generator n output pin (16bit/8bit) rstx core reset input pin rxn can can interface n rx input pin sckn usart usart n serial clock input/output pin sckn_r usart relocated usart n serial clock input/output pin sinn usart usart n serial data input pin sinn_r usart relocated usart n serial data input pin sotn usart usart n serial data output pin sotn_r usart relocated usart n serial data output pin tinn reload timer reload timer n event input pin totn reload timer reload timer n output pin ttgn ppg programmable pulse generator n trigger input pin txn can can interface n tx output pin v cc supply power supply pin v ss supply power supply pin x0 clock oscillator input pin x0a clock subclock oscillator input pin x1 clock oscillator output pin x1a clock subclock oscillator output pin
document number: 002 - 04709 rev.*c page 10 of 63 mb96610 serie s pin name feature description zinn qprc quadrature position/revolution counter unit n input pin
document number: 002 - 04709 rev.*c page 11 of 63 mb96610 serie s 5. pin circuit type pin no. i/o circuit type * pin name 1 supply avss 2 g avrh 3 k p06_3 / an3 / ppg3 4 k p06_4 / an4 / ppg4 5 k p06_6 / an6 / ppg6 6 k p06_7 / an7 / ppg7 7 i p05_0 / an8 / sin2 / int3_r1 8 k p05_1 / an9 / sot2 9 i p05_2 / an10 / sck2 10 k p05_4 / an12 / tot3 / int2_r 11 k p05_6 / an14 / int4_r 12 k p07_0 / an16 / int0 / nmi 13 b p04_0 / x0a 14 b p04_1 / x1a 15 c md 16 h p17_0 17 o debug i/f 18 m p00_0 / int8 / sck7_r / ppg0_b 19 h p00_1 / int9 / sot7_r / ppg1_b 20 m p00_2 / int10 / sin7_r 21 h p00_4 / int12 / sot8_r / ppg12_b 22 m p00_5 / int13 / sin8_r / ppg14_b 23 m p00_3 / int11 / sck8_r / ppg3_b 24 h p01_0 / tin1 / ckot1 / out0_r 25 h p01_1 / tot1 / ckotx1 / out1_r 26 h p01_4 / ppg4_b 27 m p01_5 / sin2_r / int7_r 28 h p01_6 / sot2_r / ppg6_b 29 m p01_7 / sck2_r / ppg7_b 30 h p02_0 / ppg12 / ckot1_r 31 h p02_2 / zin0 / ppg14 / ckot0_r 32 h p02_4 / ain0 / in0 / ttg0
document number: 002 - 04709 rev.*c page 12 of 63 mb96610 serie s pin no. i/o circuit type * pin name 33 c rstx 34 a x1 35 a x0 36 supply vss 37 supply vcc 38 f c 39 h p02_5 / bin0 / in1 / ttg1 / adtg_r 40 k p03_0 / ain1 / in4 / ttg4 / ttg12 / an24 41 k p03_1 / bin1 / in5 / ttg5 / ttg13 / an25 42 m p03_2 / int10_r / rx2 43 h p03_3 / tx2 44 k p03_6 / zin1 / out6 / an30 45 k p03_7 / out7 / an31 46 k p06_0 / an0 / ppg0 47 k p06_1 / an1 / ppg1 48 supply avcc *: see i/o circuit type for details on the i/o circuit types.
document number: 002 - 04709 rev.*c page 13 of 63 mb96610 serie s 6. i/o circuit type type circuit remarks a high - speed oscillation circuit: ? programmable between oscillation mode (external crystal or resonator connected to x0/x1 pins) and fast external clock input (fci) mode (external clock connected to x0 pin) ? feedback resistor = approx. 1.0m ? the amplitude: 1.8v0.15v to operate by t he internal supply voltage r fci x out 0 1 x1 x0 f c i or o sc d i sab l e
document number: 002 - 04709 rev.*c page 14 of 63 mb96610 serie s type circuit remarks b low - speed oscillation circuit shared with gpio functionality: ? feedback resistor = approx. 5.0m ? gpio functionality selectable (cmos level output (i ol = 4ma, i oh = - 4ma), automotive input with input shutdown function and programmable pull - up resistor) r fci x out 0 1 pout r nout automotive input fci or osc disable standby control for input shutdown standby control for input shutdown automotive input x1a x0a r p-ch p-ch n-ch pull-up control pull-up control pout nout p-ch p-ch n-ch
document number: 002 - 04709 rev.*c page 15 of 63 mb96610 serie s type circuit remarks c cmos hysteresis input pin f power supply input protection circuit g ? a/d converter ref+ (avrh) power supply input pin with protection circuit ? without protection circuit against v cc for pins avrh h ? cmos level output ? (i ol = 4ma, i oh = - 4ma) ? automotive input with input shutdown function ? programmable pull - up resistor p-ch n-ch p-ch n-ch standby control for input shutdown automotive input r pull-up control pout nout p-ch p-ch n-ch
document number: 002 - 04709 rev.*c page 16 of 63 mb96610 serie s type circuit remarks i ? cmos level output ? (i ol = 4ma, i oh = - 4ma) ? cmos hysteresis input with input shutdown function ? programmable pull - up resistor ? analog input k ? cmos level output ? (i ol = 4ma, i oh = - 4ma) ? automotive input with input shutdown function ? programmable pull - up resistor ? analog input m ? cmos level output ? (i ol = 4ma, i oh = - 4ma) ? cmos h ysteresis input with input shutdown function ? programmable pull - up resistor standby control for input shutdown r pull-up control pout nout p-ch p-ch n-ch analog input hysteresis input standby control for input shutdown r pull-up control pout nout p-ch p-ch n-ch analog input automotive input standby control for input shutdown h y s t e r e s i s in put r pull-up control pout nout p-ch p-ch n-ch
document number: 002 - 04709 rev.*c page 17 of 63 mb96610 serie s type circuit remarks o ? open - drain i/o ? output 25ma, vcc = 2.7v ? ttl input standby control for input shutdown t t l input r nout n-ch
document number: 002 - 04709 rev.*c page 18 of 63 mb96610 serie s 7. memory map *1: for details about user rom area, see user rom memory map f or flash devices on the following pages. *2: for ramstart addresses, see the table on the next page. *3: unused gpr banks can be used as ram area . gpr: general - purpose register the dma area is only avail able if the device contains the corresponding resource. the available ram and rom area depends on the device. ff:ffff h de:0000 h dd:ffff h 10:0000 h 0f:c000 h 0e:9000 h 01:0000 h 00:8000 h rams t a r t0* 2 00:0c00 h 00:0380 h 00:0180 h 00:0100 h 00:00f0 h 00:0000 h gpr* 3 dm a reserved peripheral reserved user rom* 1 reserved boot-rom peripheral rom/ram mirror internal ram bank0 peripheral reserved
document number: 002 - 04709 rev.*c page 19 of 63 mb96610 serie s 8. ram start addresses devices bank 0 ram size ramstart0 mb96f612 4kb 00:7200 h mb96f613 , mb96f615 10kb 00:5a00 h
document number: 002 - 04709 rev.*c page 20 of 63 mb96610 serie s 9. user rom memory map f or flash devices *: physical address area of sas - 512b is from df:0000 h to df:01ff h . others (from df:0200 h to df:1fff h ) is m irror area of sas - 512b. sector sas contains the rom configuration block rcba at cpu address df:0000 h - df:01ff h . sas can not be used for e 2 prom emulation. mb96f612 mb96f613 mb96f615 flash size flash size 32.5kb + 32kb 64.5kb + 32kb 128.5kb + 32kb ff:ffff h 3f:ffff h ff:8000 h 3f:8000 h ff:7fff h 3f:7fff h ff:0000 h 3f:0000 h fe:ffff h 3e:ffff h fe:0000 h 3e:0000 h fd:ffff h bank a of flash a sas - 512b* reserved reserved sa2 - 8kb sa1 - 8kb sa4 - 8kb sa3 - 8kb sa38 - 64kb sa39 - 64kb cpu mode address flash memory mode address reserved sa4 - 8kb sa3 - 8kb sa2 - 8kb sa1 - 8kb sas - 512b* reserved sa4 - 8kb sa3 - 8kb reserved reserved sa39 - 32kb sa39 - 64kb bank b of flash a bank a of flash a sas - 512b* sa2 - 8kb sa1 - 8kb flash size df:a000 h df:9fff h 1f:9fff h df:8000 h 1f:8000 h df:7fff h 1f:7fff h df:6000 h 1f:6000 h df:5fff h 1f:5fff h df:4000 h 1f:4000 h df:3fff h 1f:3fff h df:2000 h 1f:2000 h df:1fff h 1f:1fff h df:0000 h 1f:0000 h de:ffff h de:0000 h
document number: 002 - 04709 rev.*c page 21 of 63 mb96610 serie s 10. serial programming communication interface usart pins for flash serial programming (md = 0, debug i/f = 0, serial communication mode) mb96 610 pin number usart number normal function 7 usart2 sin2 8 sot2 9 sck2 20 usart7 sin7_r 19 sot7_r 18 sck7_r 22 usart8 sin8_r 21 sot8_r 23 sck8_r
document number: 002 - 04709 rev.*c page 22 of 63 mb96610 serie s 11. interrupt vector table vector number offset in vector table vector name cleared by dma index in icr to program description 0 3fc h callv0 no - callv instruction 1 3f8 h callv1 no - callv instruction 2 3f4 h callv2 no - callv instruction 3 3f0 h callv3 no - callv instruction 4 3ec h callv4 no - callv instruction 5 3e8 h callv5 no - callv instruction 6 3e4 h callv6 no - callv instruction 7 3e0 h callv7 no - callv instruction 8 3dc h reset no - reset vector 9 3d8 h int9 no - int9 instruction 10 3d4 h exception no - undefined instruction execution 11 3d0 h nmi no - non - maskable interrupt 12 3cc h dly no 12 delayed interrupt 13 3c8 h rc_timer no 13 rc clock timer 14 3c4 h mc_timer no 14 main clock timer 15 3c0 h sc_timer no 15 sub clock timer 16 3bc h lvdi no 16 low voltage detector 17 3b8 h extint0 yes 17 external interrupt 0 18 3b4 h - - 18 reserved 19 3b0 h extint2 yes 19 external interrupt 2 20 3ac h extint3 yes 20 external interrupt 3 21 3a8 h extint4 yes 21 external interrupt 4 22 3a4 h - - 22 reserved 23 3a0 h - - 23 reserved 24 39c h extint7 yes 24 external interrupt 7 25 398 h extint8 yes 25 external interrupt 8 26 394 h extint9 yes 26 external interrupt 9 27 390 h extint10 yes 27 external interrupt 10 28 38c h extint11 yes 28 external interrupt 11 29 388 h extint12 yes 29 external interrupt 12 30 384 h extint13 yes 30 external interrupt 13 31 380 h - - 31 reserved 32 37c h - - 32 reserved 33 378 h - - 33 reserved 34 374 h - - 34 reserved 35 370 h can2 no 35 can controller 2 36 36c h - - 36 reserved 37 368 h - - 37 reserved 38 364 h ppg0 yes 38 programmable pulse generator 0 39 360 h ppg1 yes 39 programmable pulse generator 1
document number: 002 - 04709 rev.*c page 23 of 63 mb96610 serie s vector number offset in vector table vector name cleared by dma index in icr to program description 40 35c h - - 40 reserved 41 358 h ppg3 yes 41 programmable pulse generator 3 42 354 h ppg4 yes 42 programmable pulse generator 4 43 350 h - - 43 reserved 44 34c h ppg6 yes 44 programmable pulse generator 6 45 348 h ppg7 yes 45 programmable pulse generator 7 46 344 h - - 46 reserved 47 340 h - - 47 reserved 48 33c h - - 48 reserved 49 338 h - - 49 reserved 50 334 h ppg12 yes 50 programmable pulse generator 12 51 330 h - - 51 reserved 52 32c h ppg14 yes 52 programmable pulse generator 14 53 328 h - - 53 reserved 54 324 h - - 54 reserved 55 320 h - - 55 reserved 56 31c h - - 56 reserved 57 318 h - - 57 reserved 58 314 h - - 58 reserved 59 310 h rlt1 yes 59 reload timer 1 60 30c h - - 60 reserved 61 308 h rlt3 yes 61 reload timer 3 62 304 h - - 62 reserved 63 300 h - - 63 reserved 64 2fc h rlt6 yes 64 reload timer 6 65 2f8 h icu0 yes 65 input capture unit 0 66 2f4 h icu1 yes 66 input capture unit 1 67 2f0 h - - 67 reserved 68 2ec h - - 68 reserved 69 2e8 h icu4 yes 69 input capture unit 4 70 2e4 h icu5 yes 70 input capture unit 5 71 2e0 h icu6 yes 71 input capture unit 6 72 2dc h - - 72 reserved 73 2d8 h - - 73 reserved 74 2d4 h icu9 yes 74 input capture unit 9 75 2d0 h icu10 yes 75 input capture unit 10 76 2cc h - - 76 reserved 77 2c8 h ocu0 yes 77 output compare unit 0 78 2c4 h ocu1 yes 78 output compare unit 1 79 2c0 h - - 79 reserved 80 2bc h - - 80 reserved
document number: 002 - 04709 rev.*c page 24 of 63 mb96610 serie s vector number offset in vector table vector name cleared by dma index in icr to program description 81 2b8 h ocu4 yes 81 output compare unit 4 82 2b4 h - - 82 reserved 83 2b0 h ocu6 yes 83 output compare unit 6 84 2ac h ocu7 yes 84 output compare unit 7 85 2a8 h - - 85 reserved 86 2a4 h - - 86 reserved 87 2a0 h - - 87 reserved 88 29c h - - 88 reserved 89 298 h frt0 yes 89 free - running timer 0 90 294 h frt1 yes 90 free - running timer 1 91 290 h frt2 yes 91 free - running timer 2 92 28c h frt3 yes 92 free - running timer 3 93 288 h rtc0 no 93 real time clock 94 284 h cal0 no 94 clock calibration unit 95 280 h - - 95 reserved 96 27c h - - 96 reserved 97 278 h - - 97 reserved 98 274 h adc0 yes 98 a/d converter 0 99 270 h - - 99 reserved 100 26c h - - 100 reserved 101 268 h - - 101 reserved 102 264 h - - 102 reserved 103 260 h - - 103 reserved 104 25c h - - 104 reserved 105 258 h linr2 yes 105 lin usart 2 rx 106 254 h lint2 yes 106 lin usart 2 tx 107 250 h - - 107 reserved 108 24c h - - 108 reserved 109 248 h - - 109 reserved 110 244 h - - 110 reserved 111 240 h - - 111 reserved 112 23c h - - 112 reserved 113 238 h - - 113 reserved 114 234 h - - 114 reserved 115 230 h linr7 yes 115 lin usart 7 rx 116 22c h lint7 yes 116 lin usart 7 tx 117 228 h linr8 yes 117 lin usart 8 rx 118 224 h lint8 yes 118 lin usart 8 tx 119 220 h - - 119 reserved 120 21c h - - 120 reserved 121 218 h - - 121 reserved
document number: 002 - 04709 rev.*c page 25 of 63 mb96610 serie s vector number offset in vector table vector name cleared by dma index in icr to program description 122 214 h - - 122 reserved 123 210 h - - 123 reserved 124 20c h - - 124 reserved 125 208 h - - 125 reserved 126 204 h - - 126 reserved 127 200 h - - 127 reserved 128 1fc h - - 128 reserved 129 1f8 h - - 129 reserved 130 1f4 h - - 130 reserved 131 1f0 h - - 131 reserved 132 1ec h - - 132 reserved 133 1e8 h flasha yes 133 flash memory a interrupt 134 1e4 h - - 134 reserved 135 1e0 h - - 135 reserved 136 1dc h - - 136 reserved 137 1d8 h qprc0 yes 137 quad position/revolution counter 0 138 1d4 h qprc1 yes 138 quad position/revolution counter 1 139 1d0 h adcrc0 no 139 a/d converter 0 - range comparator 140 1cc h - - 140 reserved 141 1c8 h - - 141 reserved 142 1c4 h - - 142 reserved 143 1c0 h - - 143 reserved
document number: 002 - 04709 rev.*c page 26 of 63 mb96610 serie s 12. handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the co nditions in which they are used (circuit conditions, environmental conditions, etc.). this page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your cypress semiconductor devices. 12.1 precautions for product design this section describes precautions when designing electronic equipment using semiconductor devices. ? absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. do not exceed these ratings. ? recommended operating conditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended opera ting conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering applic ation outside the listed conditions are advised to contact their sales representative beforehand. ? processing and protection of pins these precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/outp ut functions. 1. preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the dev ice, and in extreme cases leads to permanent damage of the device . try to prevent such overvoltage or over - current conditions at the design stage. 2. protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows . such conditions if pr esent for extended periods of time can damage the device. therefore, avoid this type of connection. 3. handling of unused input pins unconnected input pins with very high impedance levels can adversely affect stability of operation. such pins should be conne c ted through an appropriate resistance to a power supply pin or ground pin. ? latch - up semiconductor devices are constructed by the formation of p - type and n - type areas on a substrate. when subjected to abnormally high voltages, internal parasitic pnpn juncti ons (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. this condition is called latch - up.
document number: 002 - 04709 rev.*c page 27 of 63 mb96610 serie s caution: the occurrence of latch - up not only causes loss of rel iability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: 1. be sure that voltages applied to pins do not exceed the absolute maximum ratings. this should include att ention to abnormal noise, surge levels, etc. 2. be sure that abnormal current flows do not occur during the power - on sequence. ? observance of safety regulations and standards most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. customers are requested to observe applicable regulations and standards in the design of products. ? fail - safe design any semiconductor devices have inherently a certain rate of failure. you must pro tect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over - current levels and other abnormal operating conditions. ? precautions related to usage of devices cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). c aution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. the company will not be responsible for damages ari sing from such use without prior approval. 12.2 precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during solderin g, you should only mount under cypress 's recommended co nditions. for detailed information about mount conditions, contact your sales representative. ? lead insertion type mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the boar d, or mounting by using a socket. direct mounting onto boards normally involves processes for inserting leads into through - holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. in this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to cypress recommended mounting conditions. if socket mounting is used, differences in surface treatment of the socket cont acts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic lead s be verified before mounting.
document number: 002 - 04709 rev.*c page 28 of 63 mb96610 serie s ? surface mount type surface mount packaging has longer and thinner leads than lead - insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to op en connections caused by deformed pins, or sh orting due to solder bridges. you must use appropriate mounting techniques. cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. users are advised to mount packages in accordance with cypress r anking of recommended conditions. ? lead - free packaging caution: when ball grid array (bga) packages with sn - ag - cu balls are mounted using sn - pb eutectic soldering, junction strength may be reduced under some conditions of use. ? storage of semiconductor devi ces because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorpt ion of moisture. during mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, r educing moisture resistance and causing packages to crack. to prevent, do the following: 1. avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. store products in locations where temperature changes are slight. 2. use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5 c and 30 c . when you open dry package that recommends humidity 40% to 70% relative humidity. 3. when necessary, cypress packages semiconductor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storage. 4. avoid storing packages where they are exposed to corrosive gases or high levels of dust. ? baking packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the cypress recommended conditions for baking. condition: 125 c /24 h ? static electricity because semiconductor devices are particularly susceptible to damage by stati c electricity, you must take the following precautions: 1. maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. 2. electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 m ). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. ground all fixtures and instruments, or protect with anti - static measures. 5. avoid the use of styro foam or other highly static - prone materials for storage of completed board assemblies.
document number: 002 - 04709 rev.*c page 29 of 63 mb96610 serie s 12.3 precautions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described above. for reliable performance, do the following: 1. humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. 2. discharge of static electricity when high - voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. 3. corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. if you use devices in such conditions, con sider ways to prevent such exposure or to protect the devices. 4. radiation, including cosmic radiation most devices are not designed for environments involving exposure to radiation or cosmic radiation. users should provide shie lding as appropriate. 5. smoke, flame caution: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of cypress products in othe r special environmental conditions should consult with sales representatives.
document number: 002 - 04709 rev.*c page 30 of 63 mb96610 serie s 13. handling devices special care is required for the following when handling the device: ? latch - up prevention ? unused pins handling ? external clock usage ? notes on pll clock mode opera tion ? power supply pins ( v cc /v ss ) ? crystal oscillator and ceramic resonator circuit ? turn on sequence of power supply to a/d converter and analog inputs ? pin handling when not using the a/d converter ? notes on power - on ? stabilization of power supply voltage ? seri al communication ? mode pin (md) 13.1 latch - up prevention cmos ic chips may suffer latch - up under the following conditions: ? a voltage higher than v cc or lower than v ss is applied to an input or output pin. ? a voltage higher than the rated voltage is applied between v cc pins and v ss pins. ? the av cc power supply is applied before the v cc voltage. latch - up may increase the power supply current dramatically, causing thermal damages to the device. for the same reason, extra care is required to not let the analog power - supply voltage (av cc , avrh) exceed the digital power - supply voltage. 13.2 unused pins handling unused input pins can be left open when the input is disabled (corresponding bit of port input enable regis ter pier = 0). leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device. to prevent latch - up, they must therefore be pulled up or pulled down through resistors which should be more than 2 k ? . unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or external pull - up/pull - down resistor as described above. 13.3 external clock usage the permitted frequency range of an external clock depends on the oscillator type and configuration. see
document number: 002 - 04709 rev.*c page 31 of 63 mb96610 serie s ac characteristics for detailed modes and frequency limits. single and opposite phase external clocks must be connected as follows: 13.3.1 single phase external clock for main oscillator when using a single phase external clock for the main oscillator, x0 pin must be driven and x1 pin left open. and supply 1.8v power to the external clock. 13.3.2 single phase external clock for sub oscillator when using a single phase external clock for the sub oscillator, external clock mode must be selected and x0a/p04_0 pin must be driven. x1a/p04_1 pin can be configured as gpio. 13.3.3 opposite phase external cl ock when using an opposite phase external clock, x1 (x1a) pins must be supplied with a clock signal which has the opposite phase to the x0 (x0a) pins. supply level on x0 and x1 pins must be 1.8v. 13.4 notes on pll clock mode operation if the m icrocont r oller is operated with pll clock mode and no external oscillator is operating or no e xternal clock is supplied, the microcontroller attempts to work with the free oscillating pll. performance of this operation, however, cannot be guaranteed. 13.5 power supply pins (v cc /v ss ) it is required that all v cc - level as well as all v ss - level power supply pins are at the same potential. if there is more than one v cc or v ss level, the device may operate incorrectly or be damaged even within the guaranteed operating range. v cc and v ss pins must be connected to the device from the power supply with lowest possible impedance. the smoothing capacitor at vcc pin must use the one of a capacit y value that is larger than cs. besides this, as a measure against power supply noise, it is required to connect a bypass capacitor of about 0. 1 ? f between v cc and v ss pins as close as possible to v cc and v ss pins. 13.6 crystal oscillator and ceramic resonator circuit noise at x0, x1 pins or x0a, x1a pins might cause abnormal operation. it is requir ed to provide bypass capacitors with shortest possible distance to x0, x1 pins and x0a, x1a pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other c ircuits. it is highly recommended to provide a printed circuit board art work surrounding x0, x1 pins and x0a, x1a pins with a ground area for stabilizing the operation. it is highly recommended to evaluate the quartz/mcu or resonator/mcu system at the qua rtz or resonator manufacturer, especially when using low - q resonators at higher frequencies. x0 x1 x0 x1
document number: 002 - 04709 rev.*c page 32 of 63 mb96610 serie s 13.7 turn on sequence of power supply to a/d converter and analog inputs it is required to turn the a/d converter power supply (av cc , avrh) and analog inputs (ann) on after turning the digital power supply (v cc ) on. it is also required to turn the digital power off after turning the a/d converter supply and analog inputs off. in this case, avrh must not exceed av cc input voltage for ports shared with analog input ports also must not exceed av cc (turning the analog and digital power supplies simultaneously on or off is acceptable) 13.8 pin handling when not using the a/d converter if the a/d converter is not used, the power supply pins for a/d converter should be connected su ch as av cc = v cc av ss = avrh = v ss . 13.9 notes on power - on to prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower than 50 ? s from 0.2v to 2.7v. 13.10 stabilization of power supply voltage if the power supply voltage varies acutely even within the operation safety range of the v cc power supply voltage, a malfunction may occur. the v cc power supply voltage must therefore be stabilized. as stabilization guidelines, the power supply voltage must b e stabilized in such a way that v cc ripple fluctuations (peak to peak value) in the commercial frequencies (5 0 hz to 6 0 hz) fall within 10% of the standard v cc power supply voltage and the transient fluctuation rate becomes 0.1v/ ? s or less in instantaneous f luctuation for power supply switching. 13.11 serial communication there is a possibility to receive wrong data due to noise or other causes on the serial communication. therefore, design a printed circuit board so as to avoid noise. consider receiving of wrong data when designing the system. for example apply a checksum and retransmit the data if an error occurs. 13.12 mode pin (md) connect the mode pin directly to v cc or v ss pin . to prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the mode pin to v cc or v ss pin and provide a low - impedance connection.
document number: 002 - 04709 rev.*c page 33 of 63 mb96610 serie s 14. electrical characteristics 14.1 absolute maximum ratings parameter symbol condition rating unit remarks min max power supply voltage [ 1 ] v cc - v ss - 0.3 v ss + 6.0 v analog power supply voltage [1] av cc - v ss - 0.3 v ss + 6.0 v v cc = av cc [ 2 ] analog reference voltage [1] avrh - v ss - 0.3 v ss + 6.0 v av cc avrh, avrh av ss input voltage [1] v i - v ss - 0.3 v ss + 6.0 v v i v cc + 0.3v [ 3 ] output voltage [1] v o - v ss - 0.3 v ss + 6.0 v v o v cc + 0.3v [3] maximum clamp current i clamp - - 4.0 +4.0 ma applicab le to general purpose i/o pins [ 4 ] total maximum clamp current |i clamp | - - 13 ma applicable to general purpose i/o pins [4] "l" level maximum output current i ol - - 15 ma "l" level average output current i olav - - 4 ma "l" level maximum overall output current i ol - - 32 ma "l" level average overall output current i olav - - 16 ma "h" level maximum output current i oh - - - 15 ma "h" level average output current i ohav - - - 4 ma "h" level maximum overall output current i oh - - - 32 ma "h" level average overall output current i ohav - - - 16 ma power consumption [ 5 ] p d t a = +125c - 284 [ 6 ] mw operating ambient temperature t a - - 40 +125 [ 7 ] c storage temperature t stg - - 55 +150 c [ 1 ] : this parameter is based on v ss = av ss = 0v. [ 2 ] : av cc and v cc must be set to the same voltage. it is required that av cc does not exceed v cc and that the voltage at the analog inputs does not exceed av cc when the power is switched on. [3] : v i and v o should not exceed v cc + 0. 3 v. v i should also not exceed the specified ratings. however if the maximum current to/from a n input is limited by some means with external components, the i clamp rating supersedes the v i rating. input/ o utput voltages of standard ports depend on v cc . [4] : ? a pplicable to all general purpose i/o pins (pnn_m) . ? use within recommended operating conditions. ? use at dc voltage (current) . ? the +b signal should always be applied a limiting resistance placed between the +b signal and the m icrocontroller . ? the v alue of the limiting resistance should be set so that when the +b signal is applied the inpu t current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
document number: 002 - 04709 rev.*c page 34 of 63 mb96610 serie s ? note that when the microcontroller drive current is low, such as in the power saving modes, the +b input potential may pass through the p rotective diode and increase the potential at the v cc pin, and this may affect other devices. ? note that if a +b signal is input when the microcontroller power supply is off (not fixed at 0v), the power supply is provided from the pins, so that incomplete operation may result. ? note that if the +b input is applied during power - on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power reset. ? the debug i/f pin has only a protective diode against v ss . hence it is only permitted to input a negative clamping current (4ma). for protection against positive input voltages, use an external clamping diode which limits the input voltage to maximum 6. 0 v. sample recommended circuits: [ 5 ] : the maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the thermal conductance of the package on the pcb. the actual power dissipation depends on the customer application and can be calculated as follows: p d = p io + p int p io = (v ol ? i ol + v oh ? i oh ) (i / o load power dissipation, sum is performed on all i / o ports) p int = v cc ? (i cc + i a ) (internal power dissipation) i cc is the total core current consumption into v cc as described in the dc characteristics and depends on the selected operation mode and clock frequency and the usage of functions like flash programming. i a is the analog current consumption into av cc . [ 6 ] : worst case value for a package mounted on single layer pcb at specified t a without air flow. [ 7 ] : write/ erase to a large sector in flash memory is warranted with t a + 105c . warning : semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratin gs. do not exceed these ratings. v cc r +b input (0v to 16v) limiting resistance protective diode p-ch n-ch
document number: 002 - 04709 rev.*c page 35 of 63 mb96610 serie s 14.2 recommended operating conditions (v ss = av ss = 0v) parameter symbol value unit remarks min typ max power supply voltage v cc , av cc 2.7 - 5.5 v 2.0 - 5.5 v maintains ram data in stop mode smoothing capacitor at c pin c s 0.5 1.0 to 3.9 4.7 f 1.0 f (allowance within 50%) 3.9f (allowance within 20%) please use the ceramic capacitor or the capacitor of the frequency response of this level. the smoothing capacitor at v cc must use the one of a capacity value that is larger than c s . warning : the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditio ns, or combinations n ot represented on the data sheet. users considering application outside the listed conditions are advised to contact their representatives beforehand.
document number: 002 - 04709 rev.*c page 36 of 63 mb96610 serie s 14.3 dc characteristics 14.3.1 current r ating (v cc = av cc = 2.7v to 5.5v, v ss = av ss = 0v, t a = - 40c to + 125c) p arameter symbol pin name conditions value unit remarks min typ max power supply current in run modes [ 1 ] i ccpll vcc pll run mode with clks1/2 = clkb = clkp1/2 = 32mhz flash 0 wait (clkrc and clksc stopped) - 25 - ma t a = +25 c - - 34 ma t a = +105c - - 35 ma t a = +125c i ccmain main run mode with clks1/2 = clkb = clkp1/2 = 4mhz flash 0 wait (clkpll, clksc and clkrc stopped) - 3.5 - ma t a = +25 c - - 7.5 ma t a = +105c - - 8.5 ma t a = +125c i ccrch rc run mode with clks1/2 = clkb = clkp1/2 = clkrc = 2mhz flash 0 wait (clkmc, clkpll and clksc stopped) - 1.7 - ma t a = +25 c - - 5.5 ma t a = +105c - - 6.5 ma t a = +125c i ccrcl rc run mode with clks1/2 = clkb = clkp1/2 = clkrc = 100khz flash 0 wait (clkmc, clkpll and clksc stopped) - 0.15 - ma t a = +25 c - - 3.2 ma t a = +105c - - 4.2 ma t a = +125c i ccsub sub run mode with clks1/2 = clkb = clkp1/2 = 32khz flash 0 wait (clkmc, clkpll and clkrc stopped) - 0.1 - ma t a = +25 c - - 3 ma t a = +105c - - 4 ma t a = +125c
document number: 002 - 04709 rev.*c page 37 of 63 mb96610 serie s parameter symbol pin name conditions value unit remarks min typ max power supply current in sleep modes [1] i ccspll vcc pll sleep mode with clks1/2 = clkp1/2 = 32mhz (clkrc and clksc stopped) - 6.5 - ma t a = +25 c - - 13 ma t a = +105c - - 14 ma t a = +125c i ccsmain main sleep mode with clks1/2 = clkp1/2 = 4mhz, smcr:lpmss = 0 (clkpll, clkrc and clksc stopped) - 0.9 - ma t a = +25 c - - 4 ma t a = +105c - - 5 ma t a = +125c i ccsrch rc sleep mode with clks1/2 = clkp1/2 = clkrc = 2mhz, smcr:lpmss = 0 (clkmc, clkpll and clksc stopped) - 0.5 - ma t a = +25 c - - 3.5 ma t a = +105c - - 4.5 ma t a = +125c i ccsrcl rc sleep mode with clks1/2 = clkp1/2 = clkrc = 100khz (clkmc, clkpll and clksc stopped) - 0.06 - ma t a = +25 c - - 2.7 ma t a = +105c - - 3.7 ma t a = +125c i ccssub sub sleep mode with clks1/2 = clkp1/2 = 32khz, (clkmc, clkpll and clkrc stopped) - 0.04 - ma t a = +25 c - - 2.5 ma t a = +105c - - 3.5 ma t a = +125c
document number: 002 - 04709 rev.*c page 38 of 63 mb96610 serie s parameter symbol pin name conditions value unit remarks min typ max power supply current in timer modes [2] i cctpll vcc pll timer mode with clkpll = 32mhz (clkrc and clksc stopped) - 1800 2245 a t a = +25 c - - 3165 a t a = +105c - - 3975 a t a = +125c i cctmain main timer mode with clkmc = 4mhz, smcr:lpmss = 0 (clkpll, clkrc and clksc stopped) - 285 325 a t a = +25 c - - 1085 a t a = +105c - - 1930 a t a = +125c i cctrch rc timer mode with clkrc = 2mhz, smcr:lpmss = 0 (clkpll, clkmc and clksc stopped) - 160 210 a t a = +25c - - 1025 a t a = +105c - - 1840 a t a = +125c i cctrcl rc timer mode with clkrc = 100khz (clkpll, clkmc and clksc stopped) - 35 75 a t a = +25c - - 855 a t a = +105c - - 1640 a t a = +125c i cctsub sub timer mode with clksc = 32khz (clkmc, clkpll and clkrc stopped) - 25 65 a t a = +25 c - - 830 a t a = +105c - - 1620 a t a = +125c power supply current in stop mode [3] i cch vcc - - 20 55 a t a = +25 c - - 825 a t a = +105c - - 1615 a t a = +125c flash power down current i ccflashpd - - 36 70 a power supply current for active low voltage detector [4] i cclvd low voltage detector enabled - 5 - a t a = +25 c - - 12.5 a t a = +125c flash write/ erase current [5] i ccflash - - 12.5 - ma t a = +25 c - - 20 ma t a = +125c [ 1 ] : the power supply current is measured with a 4mhz external clock connected to the main oscillator and a 32khz external clock connected to the sub oscillator. see chapter standby mode and voltage regulator control circuit of the hardware manual for further details about voltage regulator control. current for "on chip debugger" part is not included. power supply current i n run mode does not include flash write / erase current. [ 2 ] : the power supply current in timer mode is the value when flash is in power - down / reset mode. when flash is not in power - down / reset mode, i ccflashpd must be added to the power supply current. the power supply current is measured with a 4mhz external clock connected to the main oscillator and a 32khz external clock connected to the sub oscillator. the current for "on chip debugger" part is not included. [ 3 ] : the power supply current in stop mode is the value when flash is in power - down / reset mode. when flash is not in power - down / reset mode, i ccflashpd must be added to the power supply current. [ 4 ] : when low voltage detector is enabled, i cclvd must be added to power supply current. [ 5 ] : when flash write / erase program is executed, i ccflash must be added to power supply current.
document number: 002 - 04709 rev.*c page 39 of 63 mb96610 serie s 14.3.2 pin c haracteristics ( v cc = av cc = 2.7v to 5.5v, v ss = av ss = 0v, t a = - 40c to + 125c) parameter symbol pin name conditions value unit remarks min typ max "h" level input voltage v ih port inputs pnn_m - v cc 0.7 - v cc + 0.3 v cmos hysteresis input - v cc 0.8 - v cc + 0.3 v automotive hysteresis input v ihx0s x0 external clock in "fast clock input mode" vd 0.8 - vd v vd=1.8v 0.15v v ihx0as x0a external clock in "oscillation mode" v cc 0.8 - v cc + 0.3 v v ihr rstx - v cc 0.8 - v cc + 0.3 v cmos hysteresis input v ihm md - v cc - 0.3 - v cc + 0.3 v cmos hysteresis input v ihd debug i/f - 2.0 - v cc + 0.3 v ttl input "l" level input voltage v il port inputs pnn_m - v ss - 0.3 - v cc 0.3 v cmos hysteresis input - v ss - 0.3 - v cc 0.5 v automotive hysteresis input v ilx0s x0 external clock in "fast clock input mode" v ss - vd 0.2 v vd=1.8v 0.15v v ilx0as x0a external clock in "oscillation mode" v ss - 0.3 - v cc 0.2 v v ilr rstx - v ss - 0.3 - v cc 0.2 v cmos hysteresis input v ilm md - v ss - 0.3 - v ss + 0.3 v cmos hysteresis input v ild debug i/f - v ss - 0.3 - 0.8 v ttl input "h" level output voltage v oh4 4ma type 4.5v v cc 5.5v i oh = - 4ma v cc - 0.5 - v cc v 2.7v v cc < 4.5v i oh = - 1.5ma "l" level output voltage v ol4 4ma type 4.5v v cc 5.5v i ol = +4ma - - 0.4 v 2.7v v cc < 4.5v i ol = +1.7ma v old debug i/f v cc = 2.7v i ol = +25ma 0 - 0.25 v input leak current i il pnn_m v ss < v i < v cc av ss < v i document number: 002 - 04709 rev.*c page 40 of 63 mb96610 serie s 14.4 ac characteristics 14.4.1 main clock input characteristics ( v cc = av cc = 2.7v to 5.5v, vd=1.8v0.15v, v ss = av ss = 0v, t a = - 40c to + 125c) parameter symbol pin name value unit remarks min typ max input frequency f c x0, x1 4 - 8 mhz when using a crystal oscillator, pll off - - 8 mhz when using an opposite phase external clock, pll off 4 - 8 mhz when using a crystal oscillator or opposite phase external clock, pll on input frequency f fci x0 - - 8 mhz when using a single phase external clock in fast clock input mode, pll off 4 - 8 mhz when using a single phase external clock in fast clock input mode, pll on input clock cycle t cylh - 125 - - ns input clock pulse width p wh , p wl - 55 - - ns
document number: 002 - 04709 rev.*c page 41 of 63 mb96610 serie s 14.4.2 sub clock input characteristics (v cc = av cc = 2.7v to 5.5v, v ss = av ss = 0v, t a = - 40c to + 125c) parameter symbol pin name conditions value unit remarks min typ max input frequency f cl x0a, x1a - - 32.768 - khz when using an oscillation circuit - - - 100 khz when using an opposite phase external clock x0a - - - 50 khz when using a single phase external clock input clock cycle t cyll - - 10 - - s input clock pulse width - - p wh /t cyll , p wl /t cyll 30 - 70 %
document number: 002 - 04709 rev.*c page 42 of 63 mb96610 serie s 14.4.3 built - in r c oscillation characteristics (v cc = av cc = 2.7v to 5.5v, v ss = av ss = 0v, t a = - 40c to + 125c) parameter symbol value unit remarks min typ max clock frequency f rc 50 100 200 khz when using slow frequency of rc oscillator 1 2 4 mhz when using fast frequency of rc oscillator rc clock stabilization time t rcstab 80 160 320 ? s when using slow frequency of rc oscillator (16 rc clock cycles) 64 128 256 ? s when using fast frequency of rc oscillator (256 rc clock cycles) 14.4.4 internal clock timing (v cc = av cc = 2.7v to 5.5v, v ss = av ss = 0v, t a = - 40c to + 125c) parameter symbol value unit min max internal system clock frequency (clks1 and clks2) f clks1 , f clks2 - 54 mhz internal cpu clock frequency (clkb), internal peripheral clock frequency (clkp1) f clkb , f clkp1 - 32 mhz internal peripheral clock frequency (clkp2) f clkp2 - 32 mhz
document number: 002 - 04709 rev.*c page 43 of 63 mb96610 serie s 14.4.5 operating conditions of pll (v cc = av cc = 2.7v to 5.5v, v ss = av ss = 0v, t a = - 40c to + 125c) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time t lock 1 - 4 ms for clkmc = 4mhz pll input clock frequency f plli 4 - 8 mhz pll oscillation clock frequency f clkvco 56 - 108 mhz permitted vco output frequency of pll (clkvco) pll phase jitter t pskew - 5 - +5 ns for clkmc (pll input clock) 4mhz 14.4.6 reset input (v cc = av cc = 2.7v to 5.5v, v ss = av ss = 0v, t a = - 40c to + 125c) parameter symbol pin name value unit min max reset input time t rstl rstx 10 - s rejection of reset input time 1 - s rstx 0.2v cc 0.2v cc t rstl
document number: 002 - 04709 rev.*c page 44 of 63 mb96610 serie s 14.4.7 power - on reset timing (v cc = av cc = 2.7v to 5.5v, v ss = av ss = 0v, t a = - 40c to + 125c) parameter symbol pin name value unit min typ max power on rise time t r vcc 0.05 - 30 ms power off time t off vcc 1 - - ms
document number: 002 - 04709 rev.*c page 45 of 63 mb96610 serie s 14.4.8 usart timing ( v cc = av cc = 2.7v to 5.5v, v ss = av ss = 0v, t a = - 40c to + 125c , c l =50pf ) parameter symbol pin name conditions 4.5v ? v cc < 5.5v 2.7v ? v cc < 4.5v uni t min max min max serial clock cycle time t scyc sckn internal shift clock mode 4t clkp1 - 4t clkp1 - ns sck sot delay time t slovi sckn, sotn - 20 + 20 - 30 + 30 ns sot sck delay time t ovshi sckn, sotn n t clkp1 C 20 * - n t clkp1 C 30 * - ns sin sck setup time t ivshi sckn, sinn t clkp1 + 45 - t clkp1 + 55 - ns sck sin hold time t shixi sckn, sinn 0 - 0 - ns serial clock "l" pulse width t slsh sckn external shift clock mode t clkp1 + 10 - t clkp1 + 10 - ns serial clock "h" pulse width t shsl sckn t clkp1 + 10 - t clkp1 + 10 - ns sck sot delay time t slove sckn, sotn - 2t clkp1 + 45 - 2t clkp1 + 55 ns sin sck setup time t ivshe sckn, sinn t clkp1 /2+ 10 - t clkp1 /2 + 10 - ns sck sin hold time t shixe sckn, sinn t clkp1 + 10 - t clkp1 + 10 - ns sck fall time t f sckn - 20 - 20 ns sck rise time t r sckn - 20 - 20 ns notes: ? ac characteristic in clk synchronized mode ? c l is he load capacity value of pins when testing. ? depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters. these parameters are shown in mb96 600 series hardware manual . ? t clkp1 indicates the peripheral clock 1 (clkp1), unit: ns these characteristic s only guarantee the same relocate port number. ? ? for example, the combination of sckn and sotn_r is not guaranteed. *: parameter n depends on t scyc and can be calculated as follows: ? if t scyc = 2 k t clkp1 , then n = k, where k is an integer > 2 ? if t scyc = (2 k + 1) t clkp1 , then n = k + 1, where k is an integer > 1 examples: t scyc n 4 t clkp1 2 5 t clkp1 , 6 t clkp1 3 7 t clkp1 , 8 t clkp1 4
document number: 002 - 04709 rev.*c page 46 of 63 mb96610 serie s t scyc v ol v ol v oh v oh v ih v ih v il v il t slovi t ivshi t shixi v ol sck sot sin internal shift clock mode t ovshi t slsh v ih v ih v ih v ih v il v ih v il v il v il v ol v oh t slove t r t shixe t ivshe t f sck sot sin t shsl external shift clock mode
document number: 002 - 04709 rev.*c page 47 of 63 mb96610 serie s 14.4.9 external input timing (v cc = av cc = 2.7v to 5.5v, v ss = av ss = 0v, t a = - 40c to + 125c) parameter symbol pin name value unit remarks min max input pulse width t inh , t inl pnn_m 2t clkp1 +200 (t clkp1 =1/f clkp1 )* - ns general purpose i/o adtg_r a/d converter trigger input tinn reload timer ttgn ppg trigger input inn input capture ainn, binn, zinn quadrature position/revolution counter intn, intn_r, intn_r1 200 - ns external interrupt nmi non - maskable interrupt *: t clkp1 indicates the peripheral clock1 (clkp1) cycle time except stop when in stop mode. v ih v il t inl t inh v il external input timing v ih
document number: 002 - 04709 rev.*c page 48 of 63 mb96610 serie s 14.5 a/d converter 14.5.1 electrical c haracteristics for the a/d converter (v cc = av cc = 2.7v to 5.5v, v ss = av ss = 0v, t a = - 40c to + 125c) parameter symbol pin name value unit remarks min typ max resolution - - - - 10 bit total error - - - 3.0 - + 3.0 lsb nonlinearity error - - - 2.5 - + 2.5 lsb differential nonlinearity error - - - 1.9 - + 1.9 lsb zero transition voltage v ot ann typ - 20 av ss + 0.5lsb typ + 20 mv full scale transition voltage v fst ann typ - 20 avrh - 1.5lsb typ + 20 mv compare time * - - 1.0 - 5.0 s 4.5v v cc 5.5v 2.2 - 8.0 s 2.7v v cc < 4.5v sampling time * - - 0.5 - - s 4.5v v cc 5.5v 1.2 - - s 2.7v v cc < 4.5v power supply current i a av cc - 2.0 3.1 ma a/d converter active i ah - - 3.3 a a/d converter not operated reference power supply current (between avrh and av ss ) i r avrh - 520 810 a a/d converter active i rh - - 1.0 a a/d converter not operated analog input capacity c vin ann - - 15.6 pf analog impedance r vin ann - - 2050 4.5v av cc 5.5v - - 3600 2.7v av cc < 4.5v analog port input current (during conversion) i ain ann - 0.3 - + 0.3 av ss < v ain < av cc , avrh analog input voltage v ain ann av ss - avrh v reference voltage range - avrh av cc - 0.1 - av cc v variation between channels - ann - - 4.0 lsb *: time for each channel .
document number: 002 - 04709 rev.*c page 49 of 63 mb96610 serie s 14.5.2 accuracy and s etting of the a/d converter s ampling t ime if the external impedance is too high or the sampling time too short, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting the a/d conversion precision. to satisfy the a/d conversion precision, a sufficient sampling time must be selected. the required sampling time (tsamp) depends on the external driving impedance r ext , the board capacitance of the a/d converter input pin c ext and the av cc voltage level. the following replacement model can be used for the calculation: r ext : e xternal driving impedance c ext : capacitance of pcb at a/d converter input c vin : analog input capacity (i/o, analog switch and adc are contained) r vin : analog input impedance (i/o, analog switch and adc are contained) the following approximation formula for the replacement model above can be used: tsamp = 7.62 (rext cext + (rext + r vin ) c vin ) ? do not sele ct a sampling time below the absolute minimum permitted value . (0.5 ? s for 4.5v av cc 5.5v , 1. 2 ? s for 2.7 v av cc < 4.5v) ? if the sampling time cannot be sufficient, connect a capacitor of about 0. 1 ? f to the analog input pin. ? a big external driving impedance also adversely affects the a/d conversion precision due to the pin input leakage current iil (static current before the sampling switch) or the analog input leakage current iain (total leakage current of pin input and comparator during sampling). the effect of the pin input leakage current iil cannot be compensated by an external capacitor. ? the accuracy gets worse as |avrh - av ss | becomes smaller. 14.5.3 definition of a/d convert er terms ? resolution : analog variation that is recognized by an a/d converte r. ? nonlinearity error : deviation of the actual conversion characteristics from a straight line that connects the zero transition point (0b0000000000 0b0000000001) to the full - scale transition point (0b1111111110 0b1111111111). ? differential nonlinear ity error : deviation from the ideal value of the input voltage that is required to change the output code by 1 lsb. ? total error : difference between the actual value and the theoretical value. the total error includes zero transition error, full - scale tran sition error and nonlinearity error. ? zero transition voltage: input voltage which results in the minimum conversion value. ? full scale transition voltage: input voltage which results in the maximum conversion value. sampling switch (d u r i n g s a m p l i n g : o n) c vin r vin analog i n put mcu r ext c ext source c o m p a r a t o r
document number: 002 - 04709 rev.*c page 50 of 63 mb96610 serie s nonlinearity error of digital output n = v nt - {1lsb (n - 1) + v ot } [lsb] 1lsb differential nonlinearity error of digital output n = v (n + 1) t - v nt - 1 [lsb] 1lsb 1lsb = v fst - v ot 1022 n : a/d converter digital output value. v o : voltage at which the digital output changes from 0x000 to 0x001. v fst : voltage at which the digital output changes from 0x3fe to 0x3ff. v nt : voltage at which the digital output changes from 0x(n ? 1) to 0xn.
document number: 002 - 04709 rev.*c page 51 of 63 mb96610 serie s 1lsb (ideal value) = avrh - av ss [v] 1024 total error of digital output n = v nt - {1lsb (n - 1) + 0.5lsb} 1lsb n : a/d converter digital output value. v nt : voltage at which the digital output changes from 0x(n + 1) to 0xn. v ot (ideal value) = av ss + 0.5lsb[v] v fst (ideal value) = avrh - 1.5lsb[v]
document number: 002 - 04709 rev.*c page 52 of 63 mb96610 serie s 14.6 low v oltage d etection function c haracteristics (v cc = av cc = 2.7v to 5.5v, v ss = av ss = 0v, t a = - 40c to + 125c) parameter symbol conditions value unit min typ max detected voltage [ 1 ] v dl0 cilcr:lvl = 0000 b 2.70 2.90 3.10 v v dl1 cilcr:lvl = 0001 b 2.79 3.00 3.21 v v dl2 cilcr:lvl = 0010 b 2.98 3.20 3.42 v v dl3 cilcr:lvl = 0011 b 3.26 3.50 3.74 v v dl4 cilcr:lvl = 0100 b 3.45 3.70 3.95 v v dl5 cilcr:lvl = 0111 b 3.73 4.00 4.27 v v dl6 cilcr:lvl = 1001 b 3.91 4.20 4.49 v power supply voltage change rate [ 2 ] dv/dt - - 0.004 - + 0.004 v/ s hysteresis width v hys cilcr:lvhys=0 - - 50 mv cilcr:lvhys=1 80 100 120 mv stabilization time t lvdstab - - - 75 s detection delay time t d - - - 30 s [ 1 ] : if the power supply voltage fluctuates within the time less than the detection delay time (t d ), there is a possibility that the low voltage detection will occur or stop after the power supply voltage passes the detection range. [ 2 ] : in order to perform the low voltage detection at the detection voltage (v dlx ), be sure to suppress fluctuation of the power supply voltage within the limits of the change ration of power supply voltage. t i m e v c c v dlx m i n v o l t a g e v dlx m a x d v d t d e t e c t e d v o l t a g e
document number: 002 - 04709 rev.*c page 53 of 63 mb96610 serie s rcr: l v de lo w v o l t age detection function enab l e low voltage detection function disable s t ab ili z a t i on t i m e t l v d s t a b lo w v o l t age detection function enab l e
document number: 002 - 04709 rev.*c page 54 of 63 mb96610 serie s 14.7 flash memory write/erase characteristics (v cc = av cc = 2.7v to 5.5v, v ss = av ss = 0v, t a = - 40c to + 125c) parameter conditions value unit remarks min typ max sector erase time large sector t a + 105c - 1.6 7.5 s includes write time prior to internal erase. small sector - - 0.4 2.1 s security sector - - 0.31 1.65 s word (16 - bit) write time large sector t a + 105c - 25 400 s not including system - level overheadtime. small sector - - 25 400 s chip erase time t a + 105c - 5.11 25.05 s includes write time prior to internal erase. note: while the flash memory is written or erased , shutdown of the external power (v cc ) is prohibited. in the application system where the external power (v cc ) might be shut down while writing or erasing , be sure to turn the power off by using a low voltage detection function . to put it concrete, change the external power in the range of change ration of power supply voltage ( - 0.004v/ ? s to +0.004v/ ? s ) after the external power falls below the detection voltage (v dlx ) *1 . write/erase cycles and data hold time write / erase cycles (cycle) data hold time (year) 1,000 20 [ 2 ] 10,000 10 [ 2 ] 100,000 5 [ 2 ] [ 1 ] : see " 14.6 low v oltage d etection function c haracteristics " . [2] : this value comes from the technology qualification (using arrhenius equation to translate high temperature measurements into normalized value at + 85 ? c ).
document number: 002 - 04709 rev.*c page 55 of 63 mb96610 serie s 15. e xample characteristics this characteristic is an actual value of the arbitrary sample. it is not the guaranteed value. mb96f6 1 5 0 . 0 1 0 . 1 0 1 . 0 0 1 0 . 0 0 1 0 0 . 0 0 - 5 0 0 5 0 1 0 0 1 5 0 i c c [ m a ] t a [ o c] r un m od e p ll c l o c k ( 32 m h z ) m a i n o s c . ( 4 m h z ) rc c l o c k ( 2 m h z ) rc c l o c k ( 100k h z ) s u b o s c . ( 32k h z ) ( v c c = 5 . 5 v ) 0 . 00 1 0 . 01 0 0 . 10 0 1 . 00 0 1 0 . 0 0 0 1 0 0 . 0 0 0 - 5 0 0 5 0 1 0 0 1 5 0 i c c [ m a ] t a [ o c] s l eep m od e p ll c l o c k ( 32 m h z ) m a i n o s c . ( 4 m h z ) rc c l o c k ( 2 m h z ) rc c l o c k ( 100k h z ) s u b o s c . ( 32k h z ) ( v c c = 5 . 5 v )
document number: 002 - 04709 rev.*c page 56 of 63 mb96610 serie s mb96f6 15 0 . 00 1 0 . 01 0 0 . 10 0 1 . 00 0 1 0 . 0 0 0 - 5 0 0 5 0 1 0 0 1 5 0 i c c [ m a ] t a [ o c] t i m e r m od e p ll c l o c k ( 32 m h z ) m a i n o s c . ( 4 m h z ) rc c l o c k ( 2 m h z ) rc c l o c k ( 100k h z ) s u b o s c . ( 32k h z ) ( v c c = 5 . 5 v ) 0 . 00 1 0 . 01 0 0 . 10 0 1 . 00 0 - 5 0 0 5 0 1 0 0 1 5 0 i c c [ m a ] t a [ o c] s t op m od e ( v c c = 5 . 5 v )
document number: 002 - 04709 rev.*c page 57 of 63 mb96610 serie s used setting mode selected source clock clock/regulator and flash settings run mode pll clks1 = clks2 = clkb = clkp1 = clkp2 = 32mhz main osc. clks1 = clks2 = clkb = clkp1 = clkp2 = 4mhz rc clock fast clks1 = clks2 = clkb = clkp1 = clkp2 = 2mhz rc clock slow clks1 = clks2 = clkb = clkp1 = clkp2 = 100khz sub osc. clks1 = clks2 = clkb = clkp1 = clkp2 = 32khz sleep mode pll clks1 = clks2 = clkp1 = clkp2 = 32mhz regulator in high power mode, (clkb is stopped in this mode) main osc. clks1 = clks2 = clkp1 = clkp2 = 4mhz regulator in high power mode, (clkb is stopped in this mode) rc clock fast clks1 = clks2 = clkp1 = clkp2 = 2mhz regulator in high power mode, (clkb is stopped in this mode) rc clock slow clks1 = clks2 = clkp1 = clkp2 = 100khz regulator in low power mode, (clkb is stopped in this mode) sub osc. clks1 = clks2 = clkp1 = clkp2 = 32khz regulator in low power mode, (clkb is stopped in this mode) timer mode pll clkmc = 4mhz, clkpll = 32mhz (system clocks are stopped in this mode) regulator in high power mode, flash in power - down / reset mode main osc. clkmc = 4mhz (system clocks are stopped in this mode) regulator in high power mode, flash in power - down / reset mode rc clock fast clkmc = 2mhz (system clocks are stopped in this mode) regulator in high power mode, flash in power - down / reset mode rc clock slow clkmc = 100khz (system clocks are stopped in this mode) regulator in low power mode, flash in power - down / reset mode sub osc. clkmc = 32 khz (system clocks are stopped in this mode) regulator in low power mode, flash in power - down / reset mode stop mode stopped (all clocks are stopped in this mode) regulator in low power mode, flash in power - down / reset mode
document number: 002 - 04709 rev.*c page 58 of 63 mb96610 serie s 16. o rdering information mcu with can controller part number flash memory package * mb96f612rbpmc - gse1 flash a (64.5kb) 48 - pin plastic lqfp ( lqa048 ) mb96f612rbpmc - gs - uje1 mb96f612rbpmc - gse2 mb96f612rbpmc - gs - uje2 mb96f612rbpmc - gte1 mb96f613rbpmc - gse1 flash a (96.5kb) 48 - pin plastic lqfp ( lqa048 ) mb96f613rbpmc - gs - uje1 mb96f613rbpmc - gse2 mb96f613rbpmc - gs - uje2 mb96f613rbpmc - gte1 mb96f615rbpmc - gse1 flash a (160.5kb) 48 - pin plastic lqfp ( lqa048 ) mb96f615rbpmc - gs - uje1 mb96f615rbpmc - gse2 mb96f615rbpmc - gs - uje2 mb96f615rbpmc - gte1 *: for details about package, see " package dimension ". mcu without can controller part number flash memory package * mb96f612abpmc - gse1 flash a (64.5kb) 48 - pin plastic lqfp ( lqa048 ) mb96f612abpmc - gs - uje1 mb96f612abpmc - gse2 mb96f612 abpmc - gs - uje2 mb96f612abpmc - gte1 mb96f613abpmc - gse1 flash a (96.5kb) 48 - pin plastic lqfp ( lqa048 ) mb96f613abpmc - gs - uje1 mb96f613abpmc - gse2 mb96f613abpmc - gs - uje2 mb96f613abpmc - gte1 mb96f615abpmc - gse1 flash a (160.5kb) 48 - pin plastic lqfp ( lqa048 ) mb96f615abpmc - gs - uje1 mb96f615abpmc - gse2 mb96f61 5 abpmc - g t e1 *: for details about package, see " package dimension ".
document number: 002 - 04709 rev.*c page 59 of 63 mb96610 serie s 17. package dimension l q a 0 48, 48 lead plastic low profile quad flat package package type package code lqfp 48 pin l qa048 002 - 13731 ** d i m e n si o n s s y m b o l m i n . n o m . m ax . a 1 . 7 0 a1 0 . 0 0 0 . 2 0 b 0 . 1 5 0 . 2 7 c 0 . 0 9 0 . 2 0 d 9 .00 bsc d 1 7.00 bsc e 0.50 bsc e e1 l 0 . 4 5 0 . 6 0 0 . 7 5 l 1 0 . 3 0 0 . 5 0 0 . 7 0 9.00 bsc 7.00 bsc 0 8 d1 d e 1 1 2 4 8 e e 1 4 5 7 4 5 7 3 0 . 2 0 c a - b d 3 b 0 . 1 0 c a - b d 0 . 8 0 c a - b d 8 7 5 2 2 a a' s eat i n g plane a a 1 0.2 5 1 0 b s e c t i o n a - a' c 9 l 1 l 6 0 . 8 0 c 1 4 8 1 3 2 4 3 6 2 5 3 7 1 2 1 3 2 4 2 5 3 6 3 7 7 . 0x7 . 0x1 . 7 m m l q a048 r ev * * package ou t line, 4 8 lea d lq f p
document number: 002 - 04709 rev.*c page 60 of 63 mb96610 serie s 18. major changes spansion publication number: mb96610_ds704 - 00007 page section change results revision 3.0 4 ? features changed the description of external interrupts interrupt mask and pending bit per channel interrupt mask bit per channel 23 to 26 ? handling precautions ? added a section 34 ? electrical characteristics 3. dc characteristics (1) current rating changed the conditions for i ccsrch clks1/2 = clkb = clkp1/2 = clkrc = 2mhz, clks1/2 = clkp1/2 = clkrc = 2mhz, changed the conditions for i ccsrc l clks1/2 = clkb = clkp1/2 = clkrc = 100khz clks1/2 = clkp1/2 = clkrc = 100khz 35 changed the conditions for i cctpll pll timer mode with clkp1 = 32mhz pll timer mode with clkpll = 32mhz changed the value of power supply current in timer modes i cct pll typ: 2480 a 1800 a (t a = +25c) max : 2710 a 2245 a (t a = +25c) max : 3985 a 3165 a (t a = + 10 5c) max : 4830 a 3975 a (t a = + 1 25c) changed the conditions for i cctrcl rc timer mode with clkrc = 100khz, smcr:lpmss = 0 (clkpll, clkmc and clksc stopped) rc timer mode with clkrc = 100khz (clkpll, clkmc and clksc stopped) 36 changed the annotation *2 power supply for "on chip debugger" part is not included. power supply current in run mode does not include flash write / erase current. the c urrent for "on chip debugger" part is not included. 47 5. a/d converter ( 2 ) accuracy and s etting of the a/d converter s ampling t ime ? deleted the unit [min] from approximation formula of sampling time 52 7 . flash memory write/erase characteristics changed the condition (v cc = av cc = 2.7v to 5.5v, vd=1.8v0.15v, v ss = av ss = 0v, t a = - 40c to + 125c) (v cc = av cc = 2.7v to 5.5v, v ss = av ss = 0v, t a = - 40c to + 125c)
document number: 002 - 04709 rev.*c page 61 of 63 mb96610 serie s page section change results 52 ? electrical characteristics 7 . flash memory write/erase characteristics ? changed the note while the flash memory is written or erased, shutdown of the external power (v cc ) is prohibited. in the application system where the external power (v cc ) might be shut down while writing, be sure to turn the power off by using an external voltage detector. while the flash memory is written or erased, shutdown of the external power (v cc ) is prohibited. in the application system where the external power (v cc ) might be shut down while writing or erasing, be sure to turn the power off by using a low voltage detection function. 56 ? ordering information deleted the part number mcu with can controller mb96f612rbpmc - gte2 mb96f613rbpmc - gte2 mb96f615rbpmc - gte2 mcu without can controller mb96f612abpmc - gte2 mb96f613abpmc - gte2 mb96f615abpmc - gte2 revision 3.1 - - company name and layout design change rev.*b 6 , 8, 5 8 , 59 1. product lineup 3. pin assignment 16. ordering information 17. package dimension package description modified to jedec description. fpt - 48p - m26 lqa048 5 8 16. ordering information added the following p art number. mb96f61 2 r bpmc - gs - uje 1, mb96f61 2 r bpmc - gs - uje 2, mb96f613r bpmc - gs - uje 1, mb96f613r bpmc - gs - uje 2, mb96f615r bpmc - gs - uje 1, mb96f615r bpmc - gs - uje 2, mb96f61 2 a bpmc - gs - uje 1, mb96f61 2 a bpmc - gs - uje 2 mb96f613a bpmc - gs - uje 1, mb96f613a bpmc - gs - uje 2 mb96f615a bpmc - gs - uje 1, mb96f615a bpmc - gs - uje 2 rev.*c 58 16. ordering information deleted the part number mcu without can controller mb96f615abpmc - gs - uje2
document number: 002 - 04709 rev.*c page 62 of 63 mb96610 serie s document history document title: mb96610 series , f 2 mc, 16fx , 16 - bit proprietary microcontroller document number: 002 - 04709 revision ecn orig. of change submission date description of change ** ? ksun 01/31 /201 4 migrated to cypress and assig ned document number 002 - 04709 . no change to document contents or format. *a 5146534 ksun 02 / 29 /201 6 updated to cypress template *b 5 735123 kume 0 5 / 1 5 /201 7 updated the ordering information and the package dimension for details, please see 18. major changes. *c 5 809040 miyh 0 7 / 11 /201 7 updated the ordering information for details, please see 18. major changes.
document number: 002 - 04709 rev.*c revised july 11, 2017 page 63 of 63 mb96610 serie s sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. to find the office closest to you, visit us at cypress locations . products a rm ? cortex ? microcontrollers cypress.com/a rm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress. com/iot memory cypress.com/memory microcontrollers cypress.com/mcu psoc cypress.com/psoc power management ics cypress.com/pmic touch sensing cypress.com/touch usb controllers cypress.com/ usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp | psoc 6 cypress developer community forums | wiced iot forums | projects | video | blogs | training | components technical support cypress.com/support all other trademarks or registered trademarks referenced herein are the property of their respective owners. ? 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